Priority encoders are useful logic to determine arbitrated situations that can be used in various applications. A priority encoder transfers only a single logical one bit in a highest priority position within an N-bit request signal (i.e., R) to a corresponding position an N-bit output signal (i.e., Z). Programmable priority encoders operate as multiple parallel encoders under the control of a priority signal (i.e., P).
Referring to FIG. 1, a netlist of a conventional programmable priority encoder (PPE) circuit 20 is shown. The circuit 20 uses a ripple carry implementation that creates a long timing path 22. For an N-bit signal R, the long path 22 causes a 2N−3 Boolean gate delay through the circuitry. Hence, the circuit 20 has difficulty operating at high clock speeds (i.e., >900 MHz), even for moderate values of N.
Referring to FIG. 2, a netlist of a conventional explanatory technique for a circular programmable priority encoder (CPPE) circuit 30 is shown. A path 32 in the circuit 30 forms a closed combinational loop. The loop can result in an effectively infinite delay through the circuitry in situations where the values received in the signals R and P cause the loop to oscillate.
It would be desirable to implement a programmable priority encoder and a circular programmable priority encoder without the path 22 or the path 32.